Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a convention deglitch filter. Filter 100 comprises D flip-flops 102, 104, and 106, and logic 106, where each of the flip-flops 102, 104, and 106 is clocked by clock signal CLK. In operation, data is input through the D terminal of flip-flop 102 and subsequently transferred to flip-flop 104. Logic 106 is coupled to nodes N1 and N2 and looks for spikes or glitches in the data signal or stream. Logic 106 can then provide an input to the D terminal of the flip-flop 108 based on the input from nodes N1 and N2, and the filtered data can be subsequently output at node N3.
Turning to FIG. 2, a timing diagram for an I2C system using the filter of FIG. 1 can be seen. For these I2C systems, filters, such as filter 100, are typically employed for each of the serial data SDA and serial clock SCL. For the I2C system to operate properly there is synchronization for the serial data SDA and serial clock SCL, where the corresponding rising edges of the serial clock SCL follow rising edges of the serial data SDA. As can be seen, short pulse or spike can be seen in the serial data SDA, which propagates through the filter. As a result, a rising edge on the output node N3 of the SDA filter occurs after the corresponding rising edge on output node N3 of the SCL filter, which would indicate a false start condition.
Some other examples of prior art systems are European Patent No. 1109315 and U.S. Pat. Nos. 5,001,374; 5,418,486; 6,958,641; and 7,397,292.